# Analyze the RTL (Checks for syntax) analyze -format verilog {my_design.v sub_module.v} # Elaborate (Builds the generic technology-independent design) elaborate my_design # Set the current design context current_design my_design Use code with caution. 4. Applying Constraints (The SDC File)
# Setup Variables set link_library "* standard_cell_lib.db" set target_library "standard_cell_lib.db" set symbol_library "standard_cell_lib.sdb" set search_path ". /path/to/libraries /path/to/rtl" Use code with caution. synopsys design compiler tutorial 2021
This 2021 tutorial focuses on the modern and the core commands needed to navigate the synthesis flow effectively. 1. Understanding the Synthesis Flow # Analyze the RTL (Checks for syntax) analyze
In 2021, most designs use or Topographical mode . This mode uses physical data (like floorplan info) to predict wire delays more accurately than the old "Wire Load Models." /path/to/libraries /path/to/rtl" Use code with caution
Used to resolve references (e.g., pre-existing IP blocks or pads). 3. Loading the Design
The physical cells the tool will use to build your design.
Finalizing the gate-level netlist based on constraints. 2. Setting Up Your Environment